| 000 | 00734nam a2200325Ia 4500 | ||
|---|---|---|---|
| 100 | _aCHETAN, BALARAJ and AVINASH | ||
| 650 | _aNetworks on Chip on FPGA | ||
| 520 | _aINTERNAL GUIDE: SHILPA, MVJCE | ||
| 365 | _cRS | ||
| 365 | _d1 | ||
| 942 | _cIR | ||
| 654 | _aProject | ||
| 654 | _aReport | ||
| 654 | _aon | ||
| 654 | _aa | ||
| 654 | _aDynamic | ||
| 654 | _aBuffer | ||
| 654 | _aResize | ||
| 654 | _aTechnique | ||
| 654 | _afor | ||
| 654 | _aNetworks | ||
| 654 | _aon | ||
| 654 | _aChip | ||
| 654 | _aon | ||
| 654 | _aFPGA | ||
| 654 | _aNetworks on Chip on FPGA | ||
| 245 | _aProject Report on a Dynamic Buffer Resize Technique for Networks on Chip on FPGA | ||
| 260 | _c2012 | ||
| 300 | _aIII+63 PP | ||
| 999 |
_c11693 _d11693 |
||