MALINDER KAUR and POORNIMA S <br/><br/>
Project Report on Implementation of 16 BIT Paraller 1/0 using VHDL 

 -  2004 
 - VI+70 PP 
<br/><br/> INTERNAL GUIDE: M S HIREMATH, MVJCE  EXTERNAL GUIDE: AZEEZ, LRDE 
<br/><br/><label>Subjects--Topical Terms: </label><br/>VHDL
<br/><br/><label>Subjects--Facted Index Terms: </label><br/>Project<br/>Report<br/>on<br/>Implementation<br/>16<br/>BIT<br/>Paraller<br/>1/0<br/>using<br/>VHDL<br/>VHDL