PROMOD P, RAJ KUMAR and RAJU DASAR <br/><br/>
A Project Report on FPGA Implementation of Constant False Alarm Rate Algorithm 

 -  2013 
 - 66PP 
<br/><br/> INTERNAL GUIDE       :  Arshiya Sultana   EXTERNAL GUIDE : Prayoona Valsalan and Naveen Kumar G N  USN NO                      : 1MJ09EC42, 1MJ09EC048, 1MJ09EC051  CARRIED OUT AT      :  MVJ College Of Engineering Bangalore-560067  ACC NO                     :  PR1985 
<br/><br/><label>Subjects--Topical Terms: </label><br/>FPGA Implementation of Constant False Alarm Rate Algorithm
<br/><br/><label>Subjects--Facted Index Terms: </label><br/>A<br/>Project<br/>Report<br/>on<br/>FPGA<br/>Implementation<br/>Constant<br/>Alarm<br/>Rate<br/>Algorithm<br/>FPGA Implementation of Constant False Alarm Rate Algorithm