PRAMOD P, RAJ KUMAR and RAJU DASAR <br/><br/>
A Project Report on FPGA Implementation of Sonstant False Alarm Rate Algorithm 

 -  2012-13 
 - XVII+68 PP 
<br/><br/> INTERNAL GUIDE: ARSHIYA SULTANA, MVJCE  EXTERNAL GUIDE: PARAMITA BARUA, SCIENTIST D, LRDE 
<br/><br/><label>Subjects--Topical Terms: </label><br/>FPGA Implementation of Sonstant False
<br/><br/><label>Subjects--Facted Index Terms: </label><br/>A<br/>Project<br/>Report<br/>on<br/>FPGA<br/>Implementation<br/>Sonstant<br/>Alarm<br/>Rate<br/>Algorithm<br/>FPGA Implementation of Sonstant False