CHETAN KUMAR M, BALARAJ C R AVINASH and MAHANTESHA N M <br/><br/>
Project Report on A Dynamic Buffer ResizeTechnique for Networks on Chip on FPGA 

 -  2013 
 - 63PP 
<br/><br/> INTERNAL GUIDE       :  Shilpa      EXTERNAL GUIDE : Prayoona Valsalan and Naveen Kumar G N  USN NO                      : 1MJ10EC417, 1MJ10EC408, 1MJ10EC407, 1MJ10EC419  CARRIED OUT AT      :  MVJ College Of Engineering Bangalore-560067  ACC NO                     :  PR1976 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Dynamic Buffer ResizeTechnique for Networks on Chip on FPGA
<br/><br/><label>Subjects--Facted Index Terms: </label><br/>Project<br/>Report<br/>on<br/>A<br/>Dynamic<br/>Buffer<br/>ResizeTechnique<br/>for<br/>Networks<br/>on<br/>Chip<br/>on<br/>FPGA<br/>Dynamic Buffer ResizeTechnique for Networks on Chip on FPGA