Project Report on A Dynamic Buffer ResizeTechnique for Networks on Chip on FPGA

By: CHETAN KUMAR M, BALARAJ C R AVINASH and MAHANTESHA N MMaterial type: TextTextPublication details: 2013Description: 63PPSubject(s): Dynamic Buffer ResizeTechnique for Networks on Chip on FPGA | Project | Report | on | A | Dynamic | Buffer | ResizeTechnique | for | Networks | on | Chip | on | FPGA | Dynamic Buffer ResizeTechnique for Networks on Chip on FPGASummary: INTERNAL GUIDE : Shilpa EXTERNAL GUIDE : Prayoona Valsalan and Naveen Kumar G N USN NO : 1MJ10EC417, 1MJ10EC408, 1MJ10EC407, 1MJ10EC419 CARRIED OUT AT : MVJ College Of Engineering Bangalore-560067 ACC NO : PR1976
Tags from this library: No tags from this library for this title. Log in to add tags.
    Average rating: 0.0 (0 votes)
Item type Current library Call number Status Date due Barcode
Project Report CD MVJCE CENTRAL LIBRARY
Available RC147

INTERNAL GUIDE : Shilpa EXTERNAL GUIDE : Prayoona Valsalan and Naveen Kumar G N USN NO : 1MJ10EC417, 1MJ10EC408, 1MJ10EC407, 1MJ10EC419 CARRIED OUT AT : MVJ College Of Engineering Bangalore-560067 ACC NO : PR1976

There are no comments on this title.

to post a comment.

Powered by Koha