Project Report on a Dynamic Buffer Resize Technique for Networks on Chip on FPGA

By: CHETAN, BALARAJ and AVINASHMaterial type: TextTextPublication details: 2012Description: III+63 PPSubject(s): Networks on Chip on FPGA | Project | Report | on | a | Dynamic | Buffer | Resize | Technique | for | Networks | on | Chip | on | FPGA | Networks on Chip on FPGASummary: INTERNAL GUIDE: SHILPA, MVJCE
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Item type Current library Collection Call number Status Date due Barcode
Institutional Repository MVJCE CENTRAL LIBRARY
Electronics & Communication Engineering Available PR663

INTERNAL GUIDE: SHILPA, MVJCE

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